In recent semiconductor memory devices, integration of memories becomes higher, and the area of pads occupied in a chip becomes increased. As to the arrangement of bonding pads, they are arranged on the periphery or in the center of a chip. Especially, in the latter case of a center bonding structure, longitudinal side length of the chip must be prolonged in order to arrange the pads due to the largeness of their number. On this account, it is necessary to reduce the number of wires each passing through an interstitial space between opposing pads and to shorten an interstitial distance between the pads.
A layout of a conventional semiconductor device will be explained below in reference to the accompanying drawings. FIGS. 3(a) through 3(c) are explanatory views showing a schematic layout of a conventional semiconductor device. FIG. 3(a) is a layout view showing the peripheral part of bonding pads of a center bonding structure; FIG. 3(b), a layout view showing a wire connection part of FIG. 3(a); and FIG. 3(c), an explanatory view showing a layout of another center bonding structure.
As shown in FIGS. 3(c) through 3(c) shelves 103 for arranging second peripheral circuit elements including input/output circuit element, internal voltage-dropping circuit element, logic circuit element and the like are positioned on a chip of a center bonding structure so as to sandwich bonding pads 104. A self 102 for arranging first peripheral circuit elements such as data-amplifying circuit element, word line driving circuit element and the like is positioned outside each of the shelves 103. Further, memory arrays 101 are positioned outside the shelves 102, respectively. Wires for transmitting electric signals are formed between the shelves 102 for arranging first peripheral circuit elements or between the shelves 103 for arranging second peripheral circuit elements. The shelves 102 are positioned along both sides of the pads.